Emio pins zynq

Emio pins zynq. For example,-----static int uPinNumber = 10; XGpioPs_WritePin(&psGpioInstancePtr,uPinNumber, 1);-----The code above write pin MIO10 with high level. Therefore the first EMIO pin has number 54. Our SW guys have trouble controlling the EMIO GPIO in our system. My design has able select both Gigabit Ethernet Controller(GEM0 and GEM1) using PS MIO pins. MIO pins are The label of each controller can be read to find the correct one. I have a GPIO signal routed from the PS to the PL fabric through EMIO. Question is that if I give 3. (The UART1 is also enabled, so the GPIOs fil up the rest of the MIO including pins 50 and 51) > I'm initialising the pointer like the Note: The zip file includes ASCII package files in TXT format and in CSV format. When I download the I have a custom board with and zynq7020 device where the GEM1 is passed though EMIO to the PL. I (SPI_M0_io0_o), . 600, . This tutorial shows how to do an HW design and code a SW application to make use of AMD Xilinx Zynq-7000 XADC. It provides flexibility in controlling GPIOs. When I build the linux image using petalinux 2022. 3V, but the SPI pins aren't doing what I Just search and read them. So far I have instantiated an IOBUF with the following connections. Is there a way to route an input signal(MIO) to an EMIO or is there another method? Hi @david. x Zynq UltraScale : How does the GPIO via EMIO map to the sysfs. If unneeded, it should be left floating. 2 and PetaLinux 2016. 2) When we create a new Block Design In Vivado, add ZYNQ7 and after block automation, it automatically adds "DDR" and I have the same issue that MISO of EMIO on SPI1 is not working. Note that Vivado Block Design validate will warn you with: WARNING: [#UNDEF] When using EMIO pins for SPI_0 tie SSIN High in the PL bitstream. The firmware driver uses it as a master only. I assign those two I2C signals to two pins on the carrier card (CON1 pin3 and pin5) driven by Assuming Zynq-7, please refer to the TRM (ug585) sections 20. The label of each controller can be read to find the correct one. The reason of asking this is because there 14 MIO pins on the ultra96 Mezzanine ports, I will like to use them from the PL using Xilinx Zynq-7000/ZynqMP MIO/EMIO GPIO controller node. This QSPI device has seperate RESET pin. So it seems that UG585 (ZYNQ 7000 SoC Technical Reference Manual) describes the EMIO from the PS (Processor) side of the system but doesn't give much details regarding how to use i2c1 configuration through EMIO pins in Zynq ultrascale+ MpSoC Hi, we are having petalinux project where we are going to connect BME280 sensor as slave for i2c1 which is controlled in PS via emio pins. My understanding is that pin assignment is made here which generates Hi. See the Checksum Offloading section in the Gigabit Ethernet Controller chapter in [Ref2] for information on checksum offloading in PS_GEM. Like Liked Unlike Reply. emio_spi0_m_i -> MISO. For example: cat **BEST SOLUTION** Hi @geetha. Files (0) Loading application | Technical Information Portal of the EMIO pins? The 7020 zynq provides 118 pins, the tools have to point out what is still available . I have enabled the GPIO on the MIO in the Zynq tab in EDK. There you will see that there are 4 banks of GPIO. T (SPI_M0_io0_t) ); </code>How I have some questions about using UART on PYNQ-Z2, I’m using Zynq for my first time, so I’m still new to this. xdc file does not have these (only clock, PMODs, leds, switches and buttons). In this board both UART interfaces are mapped to the EMIO, and then routed through the PL. My question is some of the data pins/lines or connected to MIO ports. However, if you use the UIO driver, you can use AXI GPIO IP. I assign those two I2C signals to two pins on the carrier card (CON1 pin3 and pin5) driven by R19 and T11 on the Zynq. For instance, there should be something like: create_clock -name SPI_CLK [get_pins -hier *PS7_i/EMIOSPI0SCLKO] -period 40; We are using Zynq-7030 and are confused by the pre-configuration weak pull-up specificaitons, the MIO boot strap mode pull requirements, and the actual pull-ups/downs placed in the PL IOB configurations. It is I believe this image is only supposed to indicate that 1) some PSU peripherals can be routed to MIO pins only, 2) some PSU peripherals can be routed to the PL only through EMIO--although I'm not sure what those are, off the top of my head, and 3) some PSU peripherals can be routed to either MIO or EMIO. 19K. For this we have to use the HP banks. The description DOES say that DIRM has to be set to write to DATA register, so one is left to wonder where the value on the emio_gpio_o pin There are 64 EMIO GPIO pins on Zynq-7000. for UART you have configured to use EMIO) can use Hi All! I’ve device based on Xilinx Zynq Ultrascale \+ ™ MPSoC. The pin is defined to have a PULLUP as well as actually having a physical pull-up on the carrier board. Some ZYNQ based FPGA boards have a PMOD or other connector connected to unused PS_MIO pins but your board doesn't. However, I recently made one very minor change to move the (only) UART port in the design off of MIO14-15 and over to EMIO pins. 3V levels. hamidnaghi1 (Member) 3 years ago. JA or JB seem to be I have a zynq 7000 Z20 connected to a Micrel KSZ8794 via the RGMII interface (But only with the RMII pins connected, so no RXER/TXER and only 2 data paths in the TX and RX) on the port 4 of the KSZ8794. That table shows which MIO pins can be used for each peripheral. This family of products integrates a feature-rich 64-bit quad-cor e or dual-core Arm® Cortex®-A53 and dual-core Arm Cortex-R5F based processing system (PS) and Xilinx programmable logic (PL) UltraScale architecture in a single device. 2 - PS MIO pullup/pulldowns are not correctly initialized. (It's important to do this for We have a Zynq UltraScale+ board (XCZU7EV-2FFVC1156) where the PWM input of a fan is connected to PS_MIO31 (B30). Then, allocated_gpios=ARCH_NR_GPIOS - base_gpio. O (SPI_M0_io1_i), . I assign those two I2C signals to two pins on the carrier card (CON1 pin3 and pin5) driven by Hello all! I have a Zynq-based system running Linux and have 2 input GPIO pins that are connected as EMIO. For this tutorial I am using Vivado 2016. As shown in Figure 3, the GMII interface connects the PHY and PS GEM through the EMIO pins. 2, I Configured the I2C, SPI, GPIO, SDIO as EMIO and made the external connection. The PS GEM block can be accessed through the PL using EMIO pins that allow GMII and management data input/output (MDIO) interfaces to be connected to the physical Sectional 14. In the case of CAN, even though I am adding it to the Zynq PL under MIO ports, and it appears in the Petalinux-generated DTS file, and it appears again in the compiled DTB that I use in the SD Card, I can't find it under the network interfaces in Linux. In all, there are Dear Xilinx Community, I have configured gpio emio pins from 54 to 79 (0 to 24) with following pins as outputs and inputs: out STD_LOGIC_VECTOR ( 0 downto 0 ); -- 54 -- 960 Hi, I need to use EMIO pins for I2C, UART, SPI and CAN peripherals due to lack of MIO pins. I am planning to use SD0 Controller (MIO[45:40]) of PS for MicroSD card. com 69965 - 2017. and need to use 2 ethernets at a time in my application. Three EMIO GPIO pins are exposed from the ZYNQ Processing System. I'm wondering if the SDIO interface pins in the Zynq IP config dialog should be set 'slow' or 'fast'? I'm using a 50MHz SD clock : Picozed board def file sets it to 'slow' : but Zedboard for example sets these to 'fast' . The format of this file is described in UG1075. 67248 - Vivado 2016. com Chapter 1: Introduction When you install the Vivado Design Suite, SDK is available as an optional software tool that you must choose to include in your installation. I feel the fact that PS MIO pins are not available to the PL is a serious limitation in how the Zynq device can be used. Zynq design and code details. Please let us know the procedure how to map as per hardware schematics point of view to PL [ I mean can i connect to any I/O of PL or dedicated I/O pins]. 3V. 8V tx-rx pins that receive the serial data converted from the USB packets through the FT2232HQ USB-UART bridge. I have connected the Zynq internal SPI bus signals in the PL to pins, and can see the correct MISO data on the pins. - If emio_gpio_o will contain a random value and emio pins are configured as inputs Is there any official Xilinx tutorial/answer regarding timing constraints of the EMIO interface between PS and PL? I am especially interested in the direct routing of signals between the EMIO interface and I/O in the PL. Hi @elliottalxan9 ,. TLDR: Does it matter what PL pins I use for the connection of SPI that has been passed Hello, I would like to control two EMIO pins from Petalinux 2016. I need to control an on-board peripheral that is connected to the PL's pins over I2C with the PS through the EMIO interface. The GPIO subsystem is documented in the kernel documentation in Documentation/gpio/. The reason is because they will be set by signals off board (to allow debug JTAG boot sometimes) and these will be connected via a voltage driving buffer. and MOSI data connect to an ILA to debug like following figure. Is there a way to route an input signal(MIO) to an EMIO or is there another method? I have also same issue; our custom board has two ethernet switch; one is connected to GEM0 and its mdio is thorugh MIO pins; other one is connected to GEM1 and its mdio is through EMIO pins. By choosing EMIO, it means that the pins are going to go to the PL instead, and you will be responsible for making them "External" and connecting to a PL pin (or other internal logic). On zynq 7000 Boot mode pin settings using MIO pins[8:2],there is a instruction to use 20kohm pull down resistor. I have connected two QSPI devices in MIO interface for 8 bit dual parallel mode operation. When I enable SPI via EMIO in Zynq UltraScale+, I can see that there are twelve pins under the SPI interface. Hi, I've an SPI core from the PL routed out to the pins via EMIO. But after looking at the zynq pinctrl code of the kernel, it seems that sdio1 cannot configure pins with pinctrl when sdio1 using Emio? How to slove it? thank you! Vivao is configured as follows: The device tree is configured as follows: zynq-7000. One substantial difference between using MIO or EMIO pins is that, if you chose EMIO pins for PS peripheral, than PL must be configured (FPGA design running) to have pins connected to the PS peripheral (they are wires through PL logic). Topics. Loading. 288 GPIO signals between the PS and PL through the EMIO interface. How i knows the exact pin number of FPGA to which this peripheral is I learn it from some examples that the pin number of MIOx of PS is x. In the configuration, I enable GPIO EMIO and select 4. The MIO banks are supplied with 3. So i made Uart instance in Zynq and route it to EMIO pins. Using Vivado 2019. The device boots only from SD memory card (SDIO 0, MIO pins 40-47). The EMIO pins go from the processoer system, to the programmable logic, and may be used however you wish. eMMC as a primary boot mode is not supported in zynq-7000. The general purpose I/O (GPIO) peripheral provides software with observation and control of up to 54 device pins via the MIO module. In the ila, i have saw the data transfer for the pin which is correspond to the emio78. From reading the technical manual for the Zynq-7000, it states that the GEM1 can output a GMII interface through EMIO pins. The big picture is that the logic value I read does not track the actual electrical value as that value changes. It is the same DEVICE_ID in XUartPs_LookupConfig and XUartPs_CfgInitialize functions that do work. 5G Ethernet PCS/PMA or SGMII core can be used as the physical media for the Ethernet in 1000BASE-X or SGMII mode. The Z-7012S and Z-7015 devices in the CLG4 85 package and the Z-7030 device in the SBG485 package are pin-t o-pin compatible. This loops-back perfectly; the software is a little tricky, but this test proves that the software all works correctly. The board has 8 user LEDs (DS44 . 1. 5. The EMIO pins follow after the MIO pins. See Vivado HDL processing_system7_0 wrapper file. setpindirection(&p,78,0); readpin(&p,78) -> always high!! In the zynq-7000, the Zybo-Master. The register bits are connected to the bridge PL side connections. You may also post of these forums, and perhaps someone will answer Remember, EMIO pins need to have constraints if you make these pins external. I2C0 is working Dear Xilinx Community, I have configured gpio emio pins from 54 to 79 (0 to 24) with following pins as outputs and inputs: out STD_LOGIC_VECTOR ( 0 downto 0 ); -- 54 -- 960 As shown in Figure 3, the GMII interface connects the PHY and PS GEM through the EMIO pins. IP AND TRANSCEIVERS; ETHERNET; VIDEO; DSP IP & TOOLS; PCIE; MEMORY INTERFACES AND NOC; SERIAL TRANSCEIVER; RF & DFE; OTHER I'm using a zynq ultrascale\+ device and I need to interface two SD cards for that one of them I have to route it through the PL using EMIO, having the the next signals: I was planning to route them to 7 PL pins, something like this: 52337 - Zynq-7000 SoC - Do the MIO pins provide termination? Number of Views 368. Let me explain how we will use the first 28 GPIO pins from Bank This section covers a simple example with an AXI GPIO, an AXI Timer with interrupt, and a PS section GPIO pin connected to a PL side pin using the EMIO interface. I have I would like to know if I can use MIO pins to route PL external ports? (without involving the PS). Due to the way CAN works as described here you would need an external board to facilitate it since all of the i/o is 3v3. We'd like to control the fan speed efficiently, which means controlling the tri-state of the IO pin with a PWM signal. Hello, I have a Zynq design with an EMIO-connected SPI master interface. This is my following workflow to blink LED: Step 1: Open Vivado and enable GPIO EMIO vector output about PS from zynq Ultrascale and connected this with an output ( see attachtment ) Step 2: Create a XDC file (Constraints) in order to define DATA_RO ALWAYS shows what is on the emio_gpio_i pins regardless of DIRM, OEN, and DATA registers. v (see the explanation in the DMA chapter) The VREF pin is dedicated and cannot be used as general I/O. The incompatibility of the RGMII interface on Zynq PS with LVCMOS33 is discovered lately. 2 release. Activation of a switch drives an LED low despite the GPIO signal being high. An alternate board can be the Inrevium FMCL-GLAN card. The Zynq-7000 chip has 118 GPIO pins available, 54 in the MIO and the remaining 64 in EMIO. Let me explain how we will use the first 28 GPIO pins from Bank 2 in our design. If the configuration vector is used, then you need to pulse _valid to change the configuration value on the fly. This GPIO controller is contained in both the Xilinx Zynq-7000 and ZynqMP (UltraScale) SoCs. The switches are connected to the MIO on pins 50, 51. The problem is that I cannot access those pins. The block diagram for the system is as shown in the following figure. I'm having problems getting two pushbutton switches on the Zedboard working (more generally the Zynq MIO). I want to routed out SPI and I2C cores from the PL to the pins via EMIO. Have a look at UG585, Zynq 700 Technical Reference Manual, section 14. Yes, there are posts/tutorials/videos on how to use Vivado to route uart/spi/i2c via EMIO to PL SelectIO pins. It is We are using Zynq xc7z020clg484-1 in a custom board. The SPI pins are mapped to EMIO pins since the SPI device is hooked to PL pins. Other pins on the same banks are doing 3. Hi, I am using a XC7Z014S and I would like to know in which state a MIO pin is, if it is not configured. This is tutorial video for how to create a gpio_emio project. 56787 - Zynq-7000 SoC - What is the state of MIO pins when holding PS_POR_B to 0? Number of Views 1. I am using Zedboard (with the Zynq device) but I would like to create a custom board for my Zynq design. I want to map this in the sysfs in Linux. 5G Ethernet PCS/PMA or serial gigabit media independent interface (SGMII) core can be assigned a fixed value in the range of 1 to 31. Related Questions . In Vivado I configured I2C to use EMIO pins. 288 GPIO signals between the PS and PL through Story. Our data inputs/outputs consume exactly all the pins of the 2 HP banks. The official Linux kernel from Xilinx. We can also assign the EMIO pins in this view, which we will address in a little while. It also export Zynq UART1 to J14 connector. The PHY address port of 1G/2. Looking at the Zybo-10 schematic, the MIO 16. Then you can use the pin planner after Synthesis to choose which PL IO pins you want them to We are using Zynq-7030 and are confused by the pre-configuration weak pull-up specificaitons, the MIO boot strap mode pull requirements, and the actual pull-ups/downs placed in the PL IOB configurations. Please can you tell me, how to configure ZynqMP's pins and define pinctrl bindings (list of phandles) in the device tree for 2018. The format of this file is described in UG865. In theory, one could use a PS GEM for bi-directional DMA of data at about 125 MiB/s. When I run XUartPs_SelfTest, it fails and return 1054. I then right click on the IIC_0 and make it an external port. My understanding is that pin assignment is made here which generates Dear community, To resolve a nasty software issue on our board featuring a Zynq 7020, we tried to setup the hardware TRACE port according to https://www. After building a project and configuring the Zynq clock and DDR, you need to select EMIO GPIO in MIO Configuration->I/O Peripherals->GPIO. ) */ XGpioPs_Write( &GpioInstance, 2 /*Bank 2*/, SAMPLE_COUNT << 1 ); /* Set start signal of the stream_tlaster module to start generation of the AXI-Stream of data coming from the XADC. In the Zynq MPSoC TRM (UG1085), search for the word "glance", then look at the "MIO Table at a Glance". Reading UG585, I have some difficulties in understanding how EMIO works in general. IOBUF sdio_buf ( . 3V and I've tied SS_In high as per the instructions in the TRM. For details, refer to Installation Requirements, page 10. As shown below, nothing ever drives these signals, and they remain high. This should be easy but I am doing something incredibly dumb - I just don't know what dumb thing I am doing. Hi, For a Zynq-7000 device the documentation suggests pulling the boot strap pins up or down to set the boot mode. Note: The SysFs driver has been tested and is working. Contribute to Xilinx/linux-xlnx development by creating an account on GitHub. Furthermore, the SPI interface can be routed via the Zynq's MIO or EMIO pins. For instance, there should be something like: create_clock -name SPI_CLK [get_pins -hier *PS7_i/EMIOSPI0SCLKO] -period 40; Its not clear how to write the timing constraints when you run the SPI interface (say SPI0) through EMIO pins into the fabric and out some general purpose fpga pins. The MIO SPI1 is also working fine (it is Dear Sir, I have designed (first Design )a Board with Zynq Z7045 FFGG900I-2 part with Schematic check list (excel sheet )has suggested many inputs according to that i have made connection concern is Dual ethernet on th PS Side, Based on the AVENT REP inputs i have made PS Side MDC and MDIO Pin conncetion directly with 2 marvell PHY Ics Like Parallel in this simplified example we have 2 pins as GPIO: One for Input, One for Output. . and other related components here. - Is there any chance to disable the MIO pullups via hardware configuration? - Where The purpose of this page is to introduce two methods for interacting with GPIO from user space on Zynq-7000 and Zynq Ultrascale+ MPSoC: the SysFs interface and the Linux kernel drivers (gpio-keys, leds-gpio). I don't know how to fix it. This timing signal should have been routed to a PL pin. Zynq 7000 ISE & EDK Tool Knowledge Base. What remains to be inserted are 3 clock input pins. Nothing found. Number of Views 369. code for spi0 for mio pins work for spi0 for emio pins? > Yes. I set the following properties on the PS7 IP block: CONFIG. Once in the PL, both PS EMIO and AXI Quad SPI pins are made external to the block diagram. E. 2 My requirement is to implement 2 ethernet controller from PS side. When I enable SPI via EMIO in Zynq UltraScale+, I [U-Boot] [PATCH 03/18] ARM: zynq: Remove sparse warnings Michal Simek [U-Boot] [PATCH 04/18] ARM: zynq: Added efuse status register Michal Simek [U-Boot] [PATCH 05/18] ARM: zynq: Do not use half memory size These MIO pins are then connected to a PHY ethernet device mounted on the PicoZed board (outside the SoC). but it is not showing. Also, just 1 of the ZedBoard's PMOD connected to PS - JE1 PMOD, the rest connected Hello, I would like to control two EMIO pins from Petalinux 2016. In the Zynq-7000 it is "gpiops_vX_X", and I guess it is the same for UltraScale. and were it is mapped. what to do. 142). It depends how you export SPI signals in Block Design, by default they are grouped together and exported as interface. Also, the PJTAG is routed via EMIO on J16 to the mezzanine board and then wired to J19. Multiple threads have addressed the "what is the internal resistor value" question for the pre-configuration pull-ups and the PS MIO by referring to the IRPU and IRPD I have a design that consists of the Zynq Processor System and the PS I2C (I2C0) driving EMIO. Or even program it so that a signal goes through an AXI GPIO and through, say, the UART pins via EMIO at the same time? I like to have a reset output from the Zynq-7000 PS second Ethernet interface (ENET1) via EMIO. My design has able select both Hello, I got a rather curious question. Block design in Vivado: Open UART0, open MIO and Emio, Emio bit width to 1, set the DDR model correctly, set FCLK to 50MHz, VIO output and EMIO input dock, at this time, no specified Emio pin, VIO output I want to add the support to linux gpio driver to use it. Or even program it so that a signal goes through an AXI GPIO and through, say, the UART pins via EMIO at the same time? I have connected the Zynq internal SPI bus signals in the PL to pins, and can see the correct MISO data on the pins. The Zynq-7000 has 54 MIO pins, not 78, and in this case to drive the EMIO signals you start at ID 54. This content is a preview of a link. This article will first experience the use of EMIO through the example of PS control PL part of the flow lamp, and then introduce the basic concepts related to EMIO. 73479 - Zynq UltraScale+ MPSoC, Vivado 2019. I/O interface is organized into six banks (3 MIO and 3 EMIO). 2) When we create a new Block Design In Vivado, add ZYNQ7 and after block automation, it automatically adds "DDR" and I have connected the Zynq internal SPI bus signals in the PL to pins, and can see the correct MISO data on the pins. github. I need to update the u-boot code to use these new MIO pins but I'm having trouble finding where this is configured. In the contraints, I have defined the pins like: set_property PACKAGE_PIN U8 [get_ports {spi0_gpio_tri_io[1]}] set_property PACKAGE_PIN U9 [get_ports Hello, I'm trying to use I2C1 through EMIO with Zynq UltraScale\+, but something is wrong and I can't see anything change through ILA or external scope. The ZynqMP has 174 pins (this can be verified by reading the SPIdev Tutorial for Zynq-7000 FPGA Devices. c. My understanding is that pin assignment is made here which generates Hi @dlisi_src (Member) , . First boot Linux, and find the base pin. In the ZYNQ processing core I enabled I2C_0 under Peripheral I/O Pins. The MIO is split into two voltage banks: MIO0 pins 0 to 15; MIO1 pins 16 to 53 Bank 0 includes the configuration input pins, which are sampled following power up. So, we don't have much of the Zynq MIO pin's available left, but got plenty of Zynq EMIO pins. There are many use cases where people would want to gain access to PS MIO pins from the PL, and not granting such access has greatly limit the power of Zynq. X-Ref Target - Figure 2 I want to test both of the I2C controllers in my ZC702. But what I want to know is, what's actually happening under the hood (of BD customization)? For example, in BD customization for my PS instance, the UART0 controller By using Vivado 2019. This example shows the usage of the driver in interrupt mode. When I enable SPI via EMIO in Zynq UltraScale+, I - Zynq boots from flash - FSBL runs, programs bitstream, and hands off to u-boot - U-boot performs its steps to launch linux. I am Also Facing the Same problem with SPI interface . 4. The buffer XUartPs_SelfTest gets shown in the photo: Expand Post. I want to connect this signal to an external bi-directional pin. We have a new version of the board that we are bringing up with the I2C1 pins moved to MIO 48 and 49. 1) to handle the input, output and tri-state control of this GPIO signal. Errors Later on, however, at the bottom of page 767 it states these GPIO pins are not connected to the MIO interface in any way shape-or-form. My requirement is to implement 2 ethernet controller from PS side. 3. Does Vivado take care of it automatically for some interface? I have SPI, I2C and DisplayPort AUX routed through EMIO directly to PL pins. > I found that the "selectio_wiz" block So I decided to delay these signals, even though the Zynq TRM recommends to connect the SDIO EMIO interface directly to the SelectIO pins. The GEM0 block is enabled while generating the hardware system in the Vivado® tools. 赞已点赞取消赞回复. 2. I have Well, as you can see those pins are not connected to anything. Number of Views 357. (Improperly interpreted Tx to be from the Zynq when it should have been referenced coming from my interface chip. The Gigabit Ethernet controller of Zynq is used in our project and is assigned to the MIO pins with RGMII interface. Lets look at I2C as example, the other I think will be configured the same. 请教个问题，目前我需要采用EMIO连接自创的IP核PIN，但PS不知道如何控制？那我还能控制一个EMIO吗？是像make external一样的控制方式吗？我采用一样的方式PS看起来没办法对一个emio进行控制，从PS侧，我还是对IO编号54操作，想进行如下操作： echo 54 Figure 1: Zynq UltraScale+ MPSoC Ethernet Interface The PS GEM block can be accessed through the PL using EMIO pins that allow GMII and management data input/output (MDIO) interfaces to be connected to the physical layer. Multiple threads have addressed the "what is the internal resistor value" question for the pre-configuration pull-ups and the PS MIO by referring to the IRPU and IRPD Yes . I have a design that consists of the Zynq Processor System and the PS I2C (I2C0) driving EMIO. In this case for SPI to function properly: PS-PL level shifters should be enabled; The PL should be 60755 - Zynq-7000 SoC – 2014. The description DOES say that DIRM has to be set to write to DATA register, so one is left to wonder where the value on the emio_gpio_o pin Designing 2 ethernets ports using GEMO and GEM1 in zynq PS side and MDIO pins selection. I2C0 is working Hi, I need to use EMIO pins for I2C, UART, SPI and CAN peripherals due to lack of MIO pins. For my case, I would want to have dedicated PL logic to be able to gain access to the gigabit Ethernet Recall on the Zybo-10 (see first pic below), the GPIO MIO has 8 pins. The following two macros define Zynq Ultrascale+. See the PS and Hello, We are building a design for the ZU9EG (xczu9eg-ffvb1156-2-i-EVAL). (The least significant EMIO GPIO pin 54 is the start/stop signal. ). emio_spi0_ss_o_n -> SS. It includes Pin definitions, Bank information, Mechanical drawings, Pin layout, and The MIO and EMIO pins are both part of the GPIO peripheral. Since I'm leaving BCM2 and BCM3 from the Raspberry Pi GPIO numbering scheme dedicated to the I2C interface, this means that the first GPIO pin in the 60755 - Zynq-7000 SoC – 2014. These IO signals can then be routed to the PL IO as we would any other signal and tied to a specific IO pin and standard using the XDC file. This selects EMIO pins by default. It also confuses people, so I will try to be diamond-clear: I have a block diagram in vivado with a Zynq MPSoC. Also, just 1 of the ZedBoard's PMOD connected to PS - JE1 PMOD, the rest connected I would like to use the SPI peripheral in the PS to communicate with an ADC that has an bidirectional SPI data pin (SDIO). How do I get one of the io ports to be MISO? The bd provides the following: spi_0_io0_io : inout STD_LOGIC; spi_0_io1_io : inout STD_LOGIC; spi_0_sck_io : inout STD_LOGIC; spi_0_ss1_o : out STD_LOGIC; spi_0_ss2_o The TRACE port gets routed via EMIO to the Mictor connector on the FMC-105. There aren't any PS pin numbers for EMIO - Only bridge registers. We will also see how to use the DMA to transfer This page focuses on Ethernet-based designs that use Zynq® UltraScale+™ devices. Article Number 000014058. com. EMIO pin number 54 Usage: output from Zynq PS; start input signal to the stream_tlaster. But what is the EMIO pin number? I want to know what the pin numbers(a jpg-file attached) are, so that I can use them in SDK jusk like the C code above. CAN communication can be reached using the Zynq processor through the emio pins on the board. 1 & 2019. 3V to Bank501 voltage (VCCO_MIO1_501), SD interface would work properly? I will connect Xilinx Zynq-7000/ZynqMP MIO/EMIO GPIO controller node. 45 The basic formula (for Zynq) is base_gpio=ARCH_NR_GPIOS - ZYNQ_GPIO_NR_GPIOS. The third GPIO signal drives ports with odd pin . One solution is to tie SSIN input to '1' (as described in Figure 17-8 in TRM) but you need to open and modify the Vivado HDL processing_system7_0 wrapper file, or export Zynq SPI pins as single signals If an existing design does not use SS0 when using MIO pins then one of the following needs to be done to ensure proper operation of the SPI in master mode. The following two macros define the numbers of RST and DC pins: #define ILI9488_RST_PIN 54 //== EMIO pin 0 #define ILI9488_DC_PIN 55 //== EMIO pin 1 As shown in Figure 3, the GMII interface connects the PHY and PS GEM through the EMIO pins. I have a MicroZed board (XC7Z020) with a breakout carrier card. 展开帖子 . Hello, during the bring-up of a board with a Zynq MPSoC (2EG) i noticed that the MIO-Pins have internal pullups enabled (Absolutely no software running yet). Can I directly access these pins from PL, like connecting to MIO pins using top file?? Regards I have a design that consists of the Zynq Processor System and the PS I2C (I2C0) driving EMIO. My FPGA connects to those LEDs via EMIO pins 71 . The bank I'm routing to is 3. I am using Zynq so the 54 is emio's 1st index. The 1G/2. 0. 1 I configure this in the PS block Then in the debug setup I add the 6 emio signals: Then from Linux I try a simple 'i2cdetect -r 1' but the ILA and external scope don't show any changed signals. :/ So I choose the "dirty" way of delaying the signals by ~ 8 ns using a high speed clock and a shift register. Also recall that on the Zybo-10, LED4 is connected to MIO pin 7 and BTN4, BTN5 are connected to MIO pins 50, 51 respectively. Article Details. And so I need help. The MIO pins are dedicated pins the SPI interfaces are hardwired to (saves the step of specifying package pins in the constraints file). Each GPIO is independentl In Tutorial 24, I covered controlling a SPI device by just taking control of the memory mapped GPIO and bit-banging the SPI without a driver. They are then sliced into three separate signals. Only solution was to use SPI0 interface for EMIO, this works ( the only change I did was to change all the wires from SPI1 to SPI0 in the block diagram). Hello everyone, I am using Zynq Ultrascale\+ MPSoC (XCZU15EG-1FFVB1156I) with QSPI and SPI (MRAM) interface via MIO. In vivado, I have configurd the EMIO GPIO pins like: I have set a width of 2, since I want to control 2 pins. See the PS and Note: The zip file includes ASCII package files in TXT format and in CSV format. My software will do that at the start, but what happens during configuration and boot with EMIO pins? I see three possibilities: - If all emio_gpio_o are 0 at power-up then I can just wire that pin to the output. So, I could use maximum of 64 PL pins as PS GPIOs. So I can use the numbers in the C code in SDK, then the software can operate the pins. PS I/O count does not include dedicated DDR calibrat ion pins. You can connect the eMMC using only the first 4 lines of data and use it a storage device. For example, ----- static int uPinNumber = 10; XGpioPs_WritePin(&psGpioInstancePtr,uPinNumber, 1 1. In the contraints, I have defined the pins like: set_property PACKAGE_PIN U8 [get_ports {spi0_gpio_tri_io[1]}] set_property PACKAGE_PIN U9 [get_ports This looks like another of the Xilinx quasi-mysteries that many ask and few (good) explanations are found. The I2C controller samples the input clock edge continuously for I am trying to write to the EMIO register to toggle output pins on the ZYNQ MPSoC+. But this does not show the Hi @elliottalxan9 ,. MIO pins can bear only IO signals from certain PSU peripherals. Currently the design has the Zynq GEMAC core connected to the Zynq GMII to RGMII core, and the RGMII ports are connected to pins in the EMIO NOT the MIO. Unfortunately, I am struggling to use the PS to drive the EMIO pins that are connected to the PL, which should drive the I2C signals. Hello, I'm trying to use I2C1 through EMIO with Zynq UltraScale\+, but something is wrong and I can't see anything change through ILA or external scope. Since IP Integrator only has I/O ports which do not have a tri-state control, I used the IP module "selectio_wiz" (v5. 53. 22K. ZedBoard have some, so called, FIXED_IO connections, which is hardwired to DDR memory, QSPI flash memory, Ethernet and etc. GPIO banks 0 & 1 are 32-bit and 22-bit respectively and connected to the MIO[31:0] and MIO[53:32] pins which are physic package banks 500 and 501. All of the above works well. It is assumed that you understand the concepts discussed in Using the Zynq SoC Processing System regarding adding the Zynq device into a Zynq Ultrascale+. 2 in a Zynq 7z020. Its not clear how to write the timing constraints when you run the SPI interface (say SPI0) through EMIO pins into the fabric and out some general purpose fpga pins. The primary reason of the difference in frequency via EMIO is the fabric routing delay. 2 and VITIS 2020. g. Zynq part number is xc7z100ffg1156-2 (active). Trending Articles. ) Using software, is it possible to swap these MIO pins? Maybe by defining them as GPIO, then having the UART going out to EMIIO and back. There are so many more MIO's for the Zynq\+ that they now show only a simple interface pin number, without a signal name. The code above write pin MIO10 with high level. 2 of the Zynq 7000 technical reference manual informs me of the following groups. However, I now desire to also utilize the ENET 1 (GEM1) controller as well. 1 and Appendix B. I have a marvell 88e1512 device connected via RGMII and a SFP. 1 versions, and I'm trying to run the SDK "Hello World" example: super simple software. 73614 - GTR precision calibration resistor The purpose of this page is to introduce two methods for interacting with GPIO from user space on Zynq-7000 and Zynq Ultrascale+ MPSoC: the SysFs interface and the Linux kernel drivers (gpio-keys, leds-gpio). Expand Post . My software can turn these LEDs on and off Ok using XGpioPs_WritePin(). but for MDIO pins, it can select only for any one of the Note: The zip file includes ASCII package files in TXT format and in CSV format. QSPI Interface Selected QSPI Part is S25FL512SAGBHVA10 . I am trying to use the sysfs interface to read the current logic value of the input pin and am seeing some unexpected behavior. In addition to our constraint file, it also has a board constraint file. GPIO[0] in the MIO starts at GPIO number 906 in Linux's Sysfs API, so GPIO[0] in the EMIO starts at GPIO number 960. Note that GPIO 0 on the Zynq port is Pin 54 for the ARM cores. An Inreviun TDS-FMCL-PoE card is used for this example. I dont want to use Level Shifter ICs interfaces. For more information about the Eclipse Connecting one of the ZYNQ PS UARTs to your PL design using the EMIO is pretty straight-forward. If I enable SPI 0, for example, there are a few options for the pins that can be used. HR = High Range I/O with support for I/O voltage f rom The official Linux kernel from Xilinx. I have given the EMIO a 32 bit width, and mapped it to my custom IP block, which based on certain pins Learn how MIO and EMIO relate and how to bring a signal out to the “real world” using the preferred PlanAhead/XPS flow. Now we are trying to design our new custom board. DATA_RO ALWAYS shows what is on the emio_gpio_i pins regardless of DIRM, OEN, and DATA registers. For example: cat The purpose of this page is to introduce two methods for interacting with GPIO from user space on Zynq-7000 and Zynq Ultrascale+ MPSoC: the SysFs interface and the Linux kernel drivers (gpio-keys, leds-gpio). Routed through the MIO multiplexer. 8V levels not 3. 21 (ENET 0), 28. does this value fixed? What are the limitation to use different resistor. 1 - Zynq clg225 package - Critical Warnings related to MIO pins in Synthesis and Implementation. emio_spi0_sclk_o -> CLK. Pins can be configured/operated using zynq_mio_* functions. 1 Boot failed when EMIO TPIU is enabled Number of Views 602 51786 - Zynq-7000 Example Design - Flashes MIO GPIO LEDs, EMIO GPIO LEDs and AXI GPIO LEDs on the ZC702. The function of each GPIO can be dynamically programmed on an individual or group basis. • Bank2: 32-bit bank controlling EMIO signals[31:0] • Bank3: 32-bit bank controlling EMIO signals[63:32] So I know that pin 54 is a valid EMIO pin. And obviously, if you use devmem, you can access PS_EMIO registers to control LEDs. How do I connect two I2C controllers together in PL? Then I can solve it by specifying the Mio pin of sdio1 through pinctrl in the device tree file. I need it to be disabled by default. 54105 - Zynq-7000 SoC ZC706 - ZC706 inconsistent pin assignments on FMC connector, Table 1-33 of UG954 (v1. See the chapter on using 1000BASE-X or SGMII PHY with Zynq-7000 SoC in [Ref3] for more information. Yes. I have attached an Image of the Zynq processor for reference. Requirements for Parallel Trace There are two standard connectors for parallel TPIU trace. I have 32 bit data lines interfaced to zynq from an external device. The GEM1 block is enabled while generating the hardware system. In order to design my schematic I need to know exactly what pins are mapped out on the Zynq, including what MIO pins are tied to each enabled peripheral. 2) July 31, 2018 www. In Vivado, I have a 1 bit GPIO enabled via the EMIO to an external LED on the board. The Zynq® UltraScale+™ MPSoC family is based on the UltraScale™ MPSoC architecture. For example, to drive the first EMIO signal routed to the programmable logic: A Zynq SoC PS GPIO pin connected to the fabric (PL) side pin using the EMIO interface . Number of Views 1. My question is then: I need to control an on-board peripheral that is connected to the PL's pins over I2C with the PS through the EMIO interface. Information on how to attach to the EMIO signals from the PL side is given in PG082. Zynq UltraScale+ devices integrate a flagship ARM® Cortex®-A53 64-bit quad-core or dual-core processor, Cortex-R5 dual-core real-time processor in PS, and PL in a single device. The diagram below shows the relationship 69965 - 2017. Interrupt: xgpiops_intr_example. In this tutorial, we’ll do things the “official” way, and use the one of the hard IP SPI controllers present on the ZYNQ chip. These mode pins share the multiuse I/O pins on the PS side of the device. after that i tried to find to which pin it is connected. PSU peripherals can use only certain MIO pins. Hi, Where can I find an example for writing data to eMMC? What setting do I need The description of problem with wiring SPI via EMIO and SS_IO pin is in TRM chapter 17. Or even program it so that a signal goes through an AXI GPIO and through, say, the UART pins via EMIO at the same time? ZedBoard have some, so called, FIXED_IO connections, which is hardwired to DDR memory, QSPI flash memory, Ethernet and etc. 3V, the SPI pins are configured as 3. Computation of gpio id as follow : We found in another thread that 338 is the base pin (not sure) Bank 0 = 0 - 25 (MIO 0 - 25) Bank 1 = 26 - 51 (MIO 26 - 51) Bank 2 = 52 - 77 (MIO 52 - 77) Bank 3 = 78 - 109 (EMIO 0 - 32) Bank 4 = 110 - 141 (EMIO 33 - 64) Bank 5 = 142 - 173 (EMIO 65 - 95) So, the pin would be base_gpio \+ offset, or 47574 - Zynq-7000, Boot - MIO Pins are not Three-Stated when ErrorLockDown Occurs. The first signal drives the card's LEDs. I have not seen any documentation that maps the interface pin numbers to interface Hi We are planning to use the some of PS peripherals to PL via EMIO. Peripherals can also send IO pins through the PL (fabric) as EMIO I choose emio 78 as a input pin and i have bound it to a specific fpga pin. through the EMIO pins. emio_spi0_m_o -> MOSI. 192 outputs (96 true outputs and 96 output enables). Linux - can consistently read from a minority of microSD cards. 78 GPIO signals for device pins. 30167 - LogiCORE 3GPP Turbo Hi. Everything is working except that both IO ports are MOSI. Description. However I would like to drive these pins high or low. In UG585 Table 6-15 it says, they are 3-state in SD card boot mode, but do they stay in 3-state? The use case is a prototyping board, where I would like to use signals, which are connected to MIOs, for another application, too. 28 for details of the registers that need to be controlled. URL Name 52336. Which pins should be used for SPI transactions? Test hardware: Positive point atom leader ZynQ development board (chip XC7Z020CLG400-2) Test software: Vivado 2020. How does this map? Solution. Note that the FMC pinout is different for each board. The Processor can only write to registers. Routing it though the EMIO allows for the user to assign them to the desired package pin on the Zynq FPGA chip. (It's a good idea When we break these signals out into the EMIO, the Zynq IP block will show them on the Zynq IP block. 1) I'm also using ZC702. It uses the interrupt capability of the GPIO to detect push button events and set the output LED based on the input. 33 (USB 0), and 40. PCW_ENET1_RESET_ENABLE {1} CONFIG. You will learn how to set gpio_emio, allocate emio pins, and finally operate the pins in SDK On my prototype Zynq board, I need to swap the RX and TX pins on a MIO UART in the PS. But in the sdk, the level of emio78 is alwasy high, can't be low. FSBL has programmed these to use EMIO "pins" 0x37 and 0x38, what are these in reference too? I have seen issues in the past where people were getting FSBL's setting WP/CD to use random MIO pins instead of the indicated EMIO pins or otherwise, and I was actually hoping that would be the issue. 1. Log In to Answer. SPI trough EMIO: SSIN is connected to EMIO and tied high in bitstream: SSIN_B=1. This has been added to the latest version of User Guide 933, Zynq-7000 PCB Design and Pin Planning Guide. PCW_ENET1_RESET_IO {EMIO} But there is no output port visible in the HDL description / instantiation template of the generated IP block. This example provides the usage of API's for reading/writing to the individual pins. But I cannot read back the values on the pins using XGpioPs_Read() or XGpioPs_ReadPin(). It interfaces both I/O pins of the SoC, which can be mapped in the system design tools (MIO pins), or SoC- internal signals between the processor system and the programmable logic part of the SoC (EMIO pins). It describes the use of the gigabit Ethernet controller (GEM) available in the Pin controller subsystem deals with enumerating and multiplexing pins, as well as configuring IO behavior of the pins such as bias pull up/down, slew rate, etc. SGMII core can be configured as MAC mode and connected to external PHY. The EMIO pins going to the FPGA fabric and from there can be connected to regular Select IO pins. The in XDC file I set up constraints to bring out these signals to PMOD2 connector of Kria Robotic Hello, I got a rather curious question. The SS_IO pin is declared as signal type inout (bidirectional). But what is the EMIO I'm wondering whether you can just route the I2C0 and I2C1 interface through EMIO pins without any special PL logic IP block? * Since SDA and SCL are open drain like signals on an I2C bus, does the Vivado tool handle the configuration of the EMIO pins? * do you need to set special constraints? > * is there any example available of an I2C interface Hi all, We have a working u-boot for a custom Zynq 7000 based board that uses I2C1 on MIO pins 12 and 13 (I think these are the default MIO pins). 58575 - 7 series - What is the state of the CCLK pin when PROG_B and INIT_B are 0? Number of Views 585. Hi @dlisi_src (Member) , . The At-A-Glance MIO table of the older Zynq-7000 showed the interface signal names for each MIO pin, on an interface-by-interface basis. From the zybo Reference manual (page 12), MIO48 and MIO48 are the 1. Linux device driver (e. We need this timing signal to be seen by logic in the PL without using software in the PS to read it. 2 version, I add the following to the device Zynq part number is xc7z100ffg1156-2 (active). The driver controls the SPI controller so whatever where the output is going The example design routes the EMIO GMII interface to FPGA I/Os to be used by an FMC card with an Ethernet PHY. I am using the ZYNQ-7010 of a RedPitaya. These registers are normally set up for you by either the FSBL or the OS device tree. Also included are on-chip memory, multiport We can also assign the EMIO pins in this view, which we will address in a little while. I was looking at the zynq 7000 diagram and noticed that the EMIO can pass through the PL. They seem like EMIO pin in Bank 3, do they? Hello, I got a rather curious question. If this is the correct one, then we know that 338 is the base pin. This pins, yo do not need to define again. the Design is OK but when it Comes to the Kernel Device list of devices "spidev" was not found i have followed the above procedure but also the spi device is not showing in the "/dev/" list can you help me with this problem /* Set sample count to EMIO GPIO pins 55-80, which are connected to the stream_tlaster module. xilinx. They seem to be able to control the tri-state but have not been able to drive values to the connected pins. We include modules for fast fpga-to-fpga communication through LVDS pairs. 1) Number of Views 705. 64 ( = 149. I see two ways: Use the waveout signal from a TTC connected to the IO pin. 4 (see IMPORTANT: note). From UG585-TRM of Zynq “Table 2-4 MIO-at-a-Glance” below, UART 0 can be set to pins 10-11, 14-15, and others. I'm using an EMIO pin to enable some peripheral power. Connecting SS_in pins to high/1 does not help. The first 32 pins are in Bank 2 (EMIO pin numbers 54 through 85). it should be gipos = <&gpio0 51 0>; correct? Expand Post. View datasheets for Zynq-7000 All Programmable SoC Overview by Xilinx Inc. UART Zynq UltraScale+ MPSoC have two high-speed UARTs (up to 1Mb/s). For instance, the number of MIO13 pin is 13, and the number of MIO16 is 16, and so on. But the ethernet PHY chip used on board supports In Zynq UltraScale device, the SPI-PS is configured to route through EMIO and the following pins are used for SPI transactions. 96 inputs. Thanks in advance 🙂 From the schematics of the board, the MIO 14 & 15 pins are connected to the FTDI chip. In our HW design, we configured two EMIO GPIO pins. Zynq UltraScale+ Package Device Pinout Files Zynq UltraScale+ Package Device Pinout Files SBVA484: SFVA625: SFRA484: SFRC784 I'm working on a custom board with a xc7z020. Hello, I need a SD or MicroSD card on my Zynq-7000 based design. IO (sdio), . exported though PS pins (MIO) or PL pins via the EMIO interface. Only the pin 7 direction is set as output in the Vivado Zynq subsystem - the other pins are set as inout. Next, Our SW guys have trouble controlling the EMIO GPIO in our system. Publication Date 5/17/2018. So it seems that UG585 (ZYNQ 7000 SoC Technical Reference Manual) describes the EMIO from the PS (Processor) side of the system but doesn't give much details regarding how to use them on the PL (Programmable Logic) side. To control In the ZYNQ processing core I enabled I2C_0 under Peripheral I/O Pins. The high level diagram looks like this: I have used the Xilinx GMII2RGMII IP to connect the GEM1 to the marvell device. Hello guys, I want to blink a external LED which is connected with a carry board via GPIO EMIO Interface with the Zynq ultrascale\+. The in XDC file I set up constraints to bring out these signals to PMOD2 connector of Kria Robotic You use the same driver to interact with the MIO-GPIO and EMIO-GPIO. Hello, I am not sure if this is the right sub-forum to post this question. GPIO banks 2 & 3 are 32-bits each and connected to the EMIO[31:0] & EMIO[63:32] pins. There are 64 EMIO GPIO pins on Zynq-7000. diwakartha1,. IF so how it is mapped inside the FPGA EMIO to PS & PL > Thanks Pench This should be easy but I am doing something incredibly dumb - I just don't know what dumb thing I am doing. There are 54 MIO GPIO pins on Zynq, numbered 0. - I have enabled 5 bits of EMIO GPIO in the I/O Peripherals pop-up of the Zynq tab inXPS and have connected the _I, _O and _T signals as three 5-bit vectors to external ports. dtsi: We have a critical timing signal which was routed on the PWB to an MIO pin on a Zynq 7000 (xc7z030). The second GPIO signal is connected to ports with even pin numbers. Zynq UltraScale+ MPSoC: Embedded Design Tutorial 9 UG1209 (v2018. This is Bank 5 pins 7. austin (Member) 12 年前. Note: An Example Design is an answer record that provides technical tips to test a Reading UG585, I have some difficulties in understanding how EMIO works in general. Also if possible I would like to know if anyone could send me an example. The ZC702 as a Xilinx product, Is supported by the webcase system (you bought it from us, we answer the question). Hello, I have a ZCU102 eval board. I was assuming this is not the case if PUDC is High - but obviously this is only valid for the PL-IOs. For Zynq UltraScale+ FPGAs, this document also provides instructions on how to use the PL portion of the device to convert the parallel interface into a serial HSSTP interface. I'm getting SPI traffic fine, but it's 1. Q : which setting is recommended for SD-card interfacing, and what exactly is the difference between 'fast' and 'slow', does this setting configure a different driver on the In our HW design, we configured two EMIO GPIO pins. I want four gpio's >When I create the wrapper I have gpio[3:0]. In all, there are We have a critical timing signal which was routed on the PWB to an MIO pin on a Zynq 7000 (xc7z030). This document outlines a number of things about both the Zynq-7000 AP SoC packages as well as pinouts. I am using the Kria KV260 Board and Designed the EMIO pins to PMOD connector . We connected the I2C's through the emio and assigned them to appropriate output pins; we then connected I2C0 and I2C1 using the MIO loopback switch on the Zynq. See the PS and SD or MicroSD card usage with Zynq 7000 Bank501 MIO pins at 3. Vivado Version is 2019. However, when the driver reads the RX data, it always reads 0x00s only. The flow of this chapter is similar to that in Using the Zynq SoC Processing System and uses the Zynq device as a base hardware design. I was able to see the new port from MPSoC, so I made it external. Unfortunately, for my needs the ZYNQ GEM software is too complicated to justify developing such an interface; easier to use an AXI streaming IP. This project walks through how to implement and use SPI in embedded Linux via the spidev kernel on the Zynq-7000 using PetaLinux 2022. That means that for this particular In the ZYNQ processing core I enabled I2C_0 under Peripheral I/O Pins. Yes . I discovered that the XC7Z010/020 only feature HR banks and thus no ODELAY2E is available. It got me thinking, is it at all possible to route the AXI GPIOs to the selected MIO pins via EMIO?. XGpioPs_SetDirectionPin () This function, use for showing which pis is Ip=nput and which pin is output and for this aim we use it. It's the SCL Frequency on EMIO: 340KHz . The problem is that the Zynq doesn't send anything to my computer. DS38). I then run synthesis and implementation and when that is done I look at I/O planning in the implementation. I'm using PlanAhead and SDK 2013. But what I want to know is, what's actually happening under the hood (of BD customization)? For example, in BD customization for my PS instance, the UART0 controller My question is where is the conversion table showing that pin 54 is connected to the package pin D19? Sectional 14. For the peripherals (UART, SPI, I2C, CAN, USB, ) that are part of Zynq micro-controller (part of PS) you can select if peripherals pins are MIO or EMIO. If you need a second UART you can export the unused PS UART to the PL though the EMIO and either connect the pins to PL logic or PL GPIO. To handled 96 GPIO in 3 EMIO banks you should map GPIO to chip’s pin by HDL design in PL logic. What is a little more confusing is Table 27-2 which implies that the value in DIRM register only effects the emio_gpio_t pins. Pin controller is a Hi, Zynq overview document states that there are 54 MIO pins but with the use of EMIO pins, it is possible to obtain up to 118 GPIO pins. Petalinux version is 2017. Outputs are 3-state capable. Their configuration is held locked until a certain value is written to the SLCR_UNLOCK register (at physical address f8000008) to unlock them. Dear all, I am developing an image for an ADRV9364-Z7020 Board with several peripherals (CAN, I2C, SPI, etc. nsnx vqk eiw dfze dvv wkvam iwnongct ypgkrm xst wccrs